A Multiphase Low Phase-Noise DCO based on Self-Timed Ring Oscillator

Abstract

This paper presents multiphase low-phase noise digitally controlled oscillators (DCOs) based on C-element self-timed ring oscillator (C-STRO) implementation. The proposed C-STRO outperforms traditional ring oscillators (ROs) by reducing gate delay variations and white noise. This results in improved phase noise performance and multiple high-resolution phases with low jitter. The C-STRO-based DCO results show that it maintains a similar size and tuning range to the conventional RO while improving phase noise. The C-STRO has several advantages over traditional STROs, including higher phase resolution, lower power consumption, reduced clock jitter, simple circuit structure, and compatibility with standard CMOS technologies. The DCO has been implemented in 65 nm CMOS technology. The proposed architecture generates a tuning range from 500MHz to 4GHz. Phase noise at 1 MHz frequency offset is from −92dBc/Hz to −105dBc/Hz. Figure of Merit (FoM) calculated as −166.2dBc/Hz, an improvement of approximately 4 dB from previously published work.