Abstract
This Radio frequencies play an important role in the electromagnetic spectrum. They are widely used in digital and analog communication, satellite communication, radars and many other applications. The filters play a very important role in RF communication hardware blocks and form a part of Sigma-Delta (Σδ) modulation technique used in Σδ ADCs. In today's reconfigurable hardware scenario, there is a high demand for reconfigurability in frequency as well as sampling rate. In this paper VLSI hardware architecture of low pass FIR filter with decimation is being proposed. This can be used in the design of a digital decimation filter for multi-rate RF applications. Here, it has been simulated for bandpass of 3.8 MHz frequency used in short wave radio. The proposed circuit is characterized for signal delay in the chain for time-sensitive applications. The speed is improved by a factor of 22% for the decimation filter compared to the basic Low pass FIR filter. The area in terms of basic logic gates is improved by 43.8% for the proposed filter. The digital architectural block is realized using Xilinx Integrated Synthesis Environment (ISE) 14.5 tool and further analyzed for FPGA implementation.
Published Version
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