Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS

Abstract

As the feature size of the nanoscale CMOS keeps scaling down, the charge sharing effect is becoming more and more prominent, and the occurrence possibility of the triple-node upset (TNU) increases obviously. Therefore, this article proposes a TNU-tolerant latch with low overhead (TTLL), which achieves a good tradeoff between reliability and design overhead. The high reliability against the TNU of the TTLL latch mainly depends on the structure of two interlocking rings and the output recovery module. Meanwhile, the clock-gated and high-speed path technology is utilized cleverly to optimize power consumption and propagation delay performance. Simulation results in the 28-nm CMOS process show that the TTLL latch has the minimum delay-power-area product (DPAP) among all reported latches for a wide range of operating conditions and under typical conditions achieves on average 1.11 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> , 10.34 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> , and 18.44 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> reductions in power, delay, and DPAP, respectively.