Low Noise Chip Scale Atomic Clock (LNCSAC)

Abstract

Chip Scale Atomic Clocks (CSAC) have provided a new capability in applications which had been previously been unrealizable due to the size, weight and power of atomic clocks. A CSAC requires approximately 100 mW of power within a 16 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> volume. This is more than an order of magnitude reduction in size, weight and power (SWaP.) Although CSAC has the accuracy and stability of atomic clocks, trade-offs in the design lead to only modest performance for Allan Deviation and Phase Noise. External phase locked loops using conventional ovenized crystal oscillators (OCXOs) can address some of these performance limitations; however the power consumption and size of the OCXO obviates the advantages of CSAC. The Low Noise CSAC utilizes an indirectly heated crystal resonator oscillator within the atomic clock's control loop to optimize Allan Deviation and Phase noise. This design approach increases the power consumption and size modestly while improving the phase noise and Allan deviation significantly. This paper will provide a brief overview of CSAC, describe the design of the LNCSAC and show performance data along with the timing capabilities of the module.