Optimization of the RF source for chip-scale cesium atomic clock

Abstract

Atomic clocks play an important role in the fields such as military, transportation and communication. As more and more applications pursue the small size and low-power consumption design, the chip-scale atomic clock (CSAC) become highly attractive in these days. The CSAC mainly includes an RF source, a physics package and a peripheral control circuit. The RF source which is related to the short-term stability of the CSAC plays a very important role in the CSAC. This paper aims to optimize the RF source with an optimized voltage-controlled oscillator (VCO) comparing with the one with a commercial SMV4596 VCO chip. The LC resonant circuit is used in the VCO design, and the phase noise achieved is lower about 7.70dB than the SMV4596 when tested at 300Hz offset. The RF source is made up of a VCO, a frequency synthesizer and a third-order loop filter. Test results show that the phase noise of the optimized RF source is about −76.24dBc/Hz@300Hz, while the phase noise of the one with SMV4596 is about −74.02dBc/Hz@300Hz. That is, the phase noise of the optimized RF source has improved about 2.22dB. The performance is much better than the spec of the chip-scale cesium atomic clock, which is −43dBc/Hz@300Hz. The short-term stability of the chip-scale atomic clock is expected to be improved if the optimized RF source would be used.