Abstract
Analysis and optimization process of single stage low power low noise amplifier (LNA) in CMOS technology has been presented. Input and output matching networks has been designed using derived analytic equations. Noise figure of LNA has been analyzed using accurate noise model for various noise contributors, including both of transistors in the cascode stage and substrate. Optimization process has been developed using the analysis results and graphical approach, to achieve simultaneous noise and power gain optimization, to prevent the power budget in the classical noise matching. Using the proposed approach, a 30GHz single stage cascode LNA has been designed and fabricated in the STMicroelectronics 90nm GP CMOS process. The designed LNA has good performance in comparison with the reported ones.
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