Low Leakage Fully Half-Select-Free Robust SRAM Cells With BTI Reliability Analysis

Abstract

This paper presents two different topologies of 11T SRAM cells with fully half-select-free robust operation for bit-interleaving implementation. The proposed 11T-1 and 11T-2 cells successfully eliminate Read disturb and Write half-select disturb and also improve the Write-ability by using power-cutoff and write “0”/ “1” only techniques. The 11T-1 and 11T-2 cells achieve $1.83 \times $ and $1.7 \times $ higher write-yield while both achieve approximately $2 \times $ higher read-yield as compared with 6T cell (at ${V}_{DD} = 0.9$ V). The proposed 11T-1 cell also shows 13.6% higher mean Write-margin (WM) compared with existing 11T cell. Both the proposed cells successfully eliminate floating node condition encountered in earlier power cut-off cells during write half-select. Monte-Carlo simulation confirms low-voltage operation without any additional peripheral assist circuits. We also present a comparative analysis of Bias Temperature Instability reliability impacting the SRAM performance in a predictive 32nm high-k metal gate CMOS technology. Under static stress, the Read Static Noise Margin (RSNM) reduces for all cells. However, 11T-1 and 11T-2 cells improve RSNM by 2.7% and 3.3% under relaxed stress of 10/90. Moreover, the proposed 11T-1 (11T-2) cell improves WM by 7.2% (13.2%), reduces write power by 28.0% (20.4%) and leakage power by 85.7% (86.9%), degrades write delay by 38.1% (23.3%) without affecting read delay/power over a period of 108 seconds (approx. 3 years). The 11T-1 (11T-2) cell exhibits 4.8% higher (2% lower) area overhead as compared to earlier 11T cell. Hence, the proposed 11T cells are an excellent choice for reliable SRAM design at nanoscale amidst process variations and transistor aging effect and can also be used in bit-interleaving architecture to achieve multi-cell upset immunity.