Design and Statistical Analysis of Low Power Robust 13T Static Random Access Memory Cell for IoT Applications

Abstract

The growth of Static Random Access Memory (SRAM) based cache memory is immensely sweeping for the current Internet-of-Things (IoT) applications. The low power and high speed SRAM cells are highly important and they play a significant role for the data computations in any IoT application. As IoT applications become the part and parcel of day-to-day life, its computations and data processing at the chip level are also increasing consistently. The SRAM cell with less power, better performance, improved stability is inevitable. As the technology node keeps on reducing, the core challenges of SRAM cell development rely on power, stability, speed and performance. This paper proposes a novel Low Power Robust (LPR13T) SRAM cell. The proposed LPR13T cell consists of 13-Transistors comparatively with less power, less delay and improved performance with other conventional cells and implemented in 45 nm CMOS technology. The average dynamic power of the proposed cell has been reduced by 84.09%, 84.06%, 53.59% and 25.93% against 6T, 8T, 10T and 11T cells respectively. An average of 83.42%, 83.48%, 49.76 and 20.21% write power has been minimized compared to 6T, 8T, 10T and 11T cells respectively and 22% average read power has been reduced against conventional 6T and 8T cells. The write delay of 17.16% and 19.33% is enhanced over 6T and 8T cells and read delay of 49.28%, 50.05%, 50.04% have been improved against 6T, 8T and 11T cells respectively. The separate read circuit with 3 transistors influences the stability improvement. The Monte-Carlo (MC) and process analysis simulations validate the efficiency and statistical performance of the proposed cell. Finally, the cell is also analyzed in terms of PVT (Process, Voltage, Temperature) variation to demonstrate that it is stable in any environment condition against temperature and voltage variation without any degradation.