Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications

Abstract

The main purpose of this paper is to achieve as low as possible leakage current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) to meet the requirements for ultra-low power (ULP) applications. The proposed methodology is based on studying the effect of the most effective FinFET design parameters that directly impact its leakage current. The parameters explored in this paper are the effective channel lengths L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> , gate stacks, gate contact materials, and gate-sidewall spacers (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sp</sub> ). The results show that utilizing a symmetrical dual-k material for 7-nm underlap tri-gate FinFETs appreciably allows a sufficient ON current and low leakage current and hence low stand by power consumption. Specifically, the effect of spacer length L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sp</sub> and LHK is investigated to get low leakage current keeping I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> as high as possible. Moreover, the effective channel length in subthreshold conduction (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) is maintained greater than the gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) and the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) is adjusted by the proper metal gate work function. The performance of the proposed nand p-FinFET devices is verified using Sentaurus TCAD simulator from Synopsys. The resulted I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> is 17 pA/μ m for n-FinFET and 14.7 pA/μm for p-FinFET which are the lowest leakage currents found in recent publications. The achieved I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio for both proposed devices is found to be 12.3 x 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> and 11 x 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> , respectively, which are comparable to the published data. These parameters are obtained for an appropriate choice of L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sp</sub> = 10 nm and L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HK</sub> = 5 nm. In addition, the short channel effects variations with LHK have been investigated.