Investigation of Sidewall High-k Interfacial Layer Effect in Gate-All-Around Structure

Abstract

In this article, structure optimization of high- ${k}$ interfacial layer (IL), deposited between the gate and the gate sidewall spacer, was performed in a 5-nm node nanosheet field-effect transistor (NSFET). High- ${k}$ IL can be formed during the high- ${k}$ gate dielectric and metal gate (HKMG) with gate-last process. By optimizing the structure of thickness of high- ${k}$ IL ( ${T}_{\text {hk}}$ ) with gate length ( ${L}_{\text {G}}$ ), spacer length ( ${L}_{\text {ext}}$ ), and source/drain (S/D) length ( ${L}_{\text {S/D}}$ ), improved electrical performances were obtained. By optimizing ${T}_{\text {hk}}$ with properly adjusted ${L}_{\text {G}}$ , ${L}_{\text {ext}}$ , and ${L}_{\text {S/D}}$ , highly saturated ON-/OFF-current ratio ( ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) was obtained with appropriate drain-induced barrier lowering (DIBL). Besides, reduced intrinsic gate delay ( ${C}_{\text {gg}}$ ) properties and OFF-state leakage current were identified. In addition, the reason of increased OFF-state leakage, which can be shown when ${L}_{\text {ext}}$ shrinks with extending ${T}_{\text {hk}}$ , was also investigated. Finally, the optimized electrical characteristics were obtained when ${T}_{\text {hk}}$ is adjusted with ${L}_{\text {G}}$ and ${L}_{\text {S/D}}$ . The power was reduced about 27% with the same performance and 18% enhanced performance was obtained when ${T}_{\text {hk}}$ is optimized through ${L}_{\text {G}}$ . On the contrary, reduced OFF-state leakage current and DIBL were confirmed in the case of optimization point with ${L}_{\text {S/D}}$ , which result in lower static power. Based on this comparison, optimization method and guideline for high- ${k}$ IL was proposed.