Low Latency Hybrid CORDIC Algorithm

Abstract

CORDIC (COordinate Rotational DIgital Computer) has gained momentum for decades because of its less hardware complexity in real time applications such as communication systems, signal and image processing. The main drawbacks of CORDIC algorithm are increased number of iterations, scale factor calculation and compensation. Researchers have worked to reduce the latency in terms of number of iterations and minimize the critical path with redundant arithmetic and fast adders. Some researchers have proposed algorithms to reduce the number of iterations to ${\mbi{n}}/{\bf 2}$ plus additional iterations including rotation and scale factor calculation and compensation for ${\mbi{n}}$ bit precision. However, to the knowledge of the authors, no further reduction of number of iterations has been addressed. In this context, the authors have proposed a new hybrid CORDIC algorithm which reduces the iteration to $({\bf 3}{\mbi{n}}/{\bf 8}) + {\bf 1}$ for ${\mbi{n}}$ bit precision including the scale factor calculation and compensation. The proposed algorithm and its first order architecture have been compared with the existing low latency CORDIC algorithms in terms of iterations, hardware complexity and critical delay. The scope of this work is to present a novel hybrid CORDIC algorithm along with first order hardware architecture.