Low K CMOS65 ball grid array 47 μm pitch wire bonding process development

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With driving interconnect dimensions to ever-smaller sizes, the RC delay becomes the dominant factor to impact IC performance. The RC delay time is controlled by the resistance of the metal lines in the interconnect structure of an IC, and the capacitance between the metal lines. To reduce RC delay, copper interconnects were introduced to replace aluminum. At the same time, the low K material has been widely used to replace the traditional SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> inter-layer dielectric. The introduction of low k material into wafer technology brings new challenges on assembly wire bonding process. Coupling with low k dielectric material is the continuing dimension shrinkage in bond pad size and pitch. In this paper, a CMOS65 nm low k device with 47um fine pitch was designed as test vehicle in developing the wire bond process capability on BGA package. Gold wire type, bonding capillary, and wire bonding parameters, were selected as critical factors in this study. This paper describes the key 1st bond parameter optimization on CMOS65 low K device. Different gold wire type (2N, 3N) and different capillary from different vendors were studied. The Newly- designed capillary from SPT aimed to improve wire stitch pull strength was also studied to improve 2N gold wire 2nd bond stitch bond which have weak stitch bond strength result from its big hardness. Critical responses such as Ball size, Ball height / bonded ball diameter ratio, bonded ball placement, wire pull strength, ball shear strength, and stitch pull strength were studied to understand the wire bonding effect of low k and 47 μm pad pitch. DOE (Design of Experiment) and RSM (response surface methodology) was used to optimize the wire bond process. Thermal aging test coupled with wire pull and ball shear test and their corresponding failure mode were studied. The IMC (Inter Metallic Coverage) of the Au-Al was also tested. The optimized process window/recipe had passed package reliability test with C65 low K device with 47 mum fine pitch.