Abstract
Built In Self-Test (BIST) is widely used test methodology for its testing cost, testing time and online testing capability. Traditional BIST suffers with high test hardware overhead which is due to presence of on-chip test blocks like TPG, analyzer, ROM etc. In this paper a low hardware cost BIST is proposed, which eliminates the requirement of external TPG by reconfiguring the available scan chains as TPG and ensures the testability of combo logic present in the reconfigurable scan chains. The proposed BIST is tested with standard ISCAS benchmark circuits and the experimental results shows that the proposed BIST averagely reduces the area overhead by 13.16 % and power overhead by 14.32 %.
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