Lowering the Cost of Test: ATPG vs. BIST

Abstract

Today, full-scan design-for-test (DFT) in conjunction with combinational automatic test pattern generation (ATPG) is the most common and scalable way to achieve high manufacturing defect coverage. The methodologies and tools to support such flows are quite mature and are well accepted within the design community. However, built-in self test (BIST) continues to gain acceptance as an alternative approach for manufacturing test. As economic considerations become more important in choosing a test methodology, key arguments made for BIST are the minimal tester memory required to run such tests and easily testable IP cores. However, traditional ATPG approaches offer more design flexibility and usually deliver shorter test times and higher measured stuck-at fault coverage. Adding to the decision complexity, devices are often tested on large pin count, very high performance automatic test equipment (ATE), and this ultimately drives the cost of test. Neither of these techniques fundamentally require such sophisticated (and expensive!) ATE capabilities, but how can both ATPG and BIST be ultimately exploited to lower the ATE requirements, and thus the cost of test? And which methodology will emerge the winner?