Low-Frequency Noise Assessment of Work Function Engineering Cap Layers in High-k Gate Stacks

C Claeys,R Ritzenthaler,T Schram,N Horiguchi,H Arimura,E Simoen

doi:10.1149/2.0221902jss

C Claeys, R Ritzenthaler + Show 4 more

Open Access

https://doi.org/10.1149/2.0221902jss

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Abstract

Engineering the effective work function of scaled-down devices is commonly achieved by the implementation of capping layers in the gate stack. Typical cap layers are Al2O3 for pMOSFETs and La-oxide or Mg for nMOSFETs. Besides introducing a dipole layer at the SiO2/high-κ interface, the in-diffusion of the metal ions may lead to either passivation or generation of traps in the SiO2/high-κ layer. This paper uses low frequency noise studies to determine the impact of capping layers on the quality of the SiO2/HfO2 gate stacks. The influence on the trap profiles of different types of cap layers, different locations of the cap layer (below or on top of the HfO2 dielectric) and the impact of different thermal budgets, typically used for the fabrication of Dynamic Random Access Memory (DRAM) logic devices, are investigated. The differences between several metal oxides are outlined and discussed.

Highlights

Methodology to Determine Trap Parameters from Noise StudiesW and L are the device width and length, respectively, CEOT is the capacitance density (F/cm2) corresponding with the Equivalent Oxide Thickness (EOT), f is the frequency, SVGfb is the input-referred voltage noise at flatband voltage and αt is the attenuation factor of the electron wave function in the gate oxide
The trap behavior studied here, but all the different performance parameters have to be taken into account for selecting the most appropriate threshold voltage tuning approach for a particular application

Summary

Methodology to Determine Trap Parameters from Noise Studies

W and L are the device width and length, respectively, CEOT is the capacitance density (F/cm2) corresponding with the Equivalent Oxide Thickness (EOT), f is the frequency, SVGfb is the input-referred voltage noise at flatband voltage and αt is the attenuation factor of the electron wave function in the gate oxide The latter is for an nMOSFET given by[15,16] αt = 2 2qmox it [2]. A 1/f noise spectrum can be converted in an oxide trap density profile as follows: Eq 1 transforms the noise PSD into an Not (cm−3 eV−1), while Eq 3 converts the frequency axis into a trap depth with respect to the Si/SiO2 interface. As this analysis is only feasible for RTN, the trap density profiles will be derived from the 1/f noise spectra under the elastic tunneling assumption

Impact Capping Layer on Low Frequency Noise Performance

AlO below x x

GS T

Summary