Low-field bulk defect generation during uniform carrier injection into the gate insulator of insulated gate field effect transistors at various temperatures

Abstract

Low-field electron injection of up to 1019 e/cm2 across the Si-SiO2 interface into the gate insulator of an n-channel insulated gate field effect transistor using an optically assisted hot electron injection technique was conducted from room temperature down to 100K. It was found that the room temperature data could be modeled quite accurately by attributing all of the observed ΔVt to generation of negatively charged defects whose generation follows a power law. At reduced temperatures, “structure” in the observed data indicated the presence of one shallow first order trap. In this case, a combination of a power law generation term and a single first order trap cross section was used, and is needed, to accurately model the data. It was also found that trap generation is enhanced significantly as the temperature is reduced. Threshold voltage shifts were shown by charge pumping measurements not to be associated with interface state generation under the low-field conditions employed. The results presented here indicate that even at very low applied oxide fields (1 MV/cm) hot electron injection not only results in the filling of existing traps, but also in the generation of new charged bulk defects whose generation rate increases as the temperature is reduced, or the injection current density is increased. These results also raise questions about some of the reports of small cross section trapping centers, ≤10−17 cm2, since these were typically characterized by applying a only first order trapping model to high field and/or high current density injection data. Such aggressive injection conditions could very easily have resulted in the generation of charged bulk defects which could then be erroneously identified as one or more small cross section traps.