Abstract

Intrinsic and generated bulk defects in the gate insulator of silicon insulated gate field effect transistors were examined using a continuous forward-bias pulsed injection technique to inject up to 1017 e/cm2 at 293 and 100 K, for insulator thicknesses ranging between 5.4 and 50.5 nm. The amount of trapping observed at 100 K was about 30 times greater than that at 293 K. The additional trapping at the reduced temperature was determined to come from two sources. One is trapping by existing shallow bulk defects, and the other is an increase in the density of generated bulk defects. The defect generation process is thought to be related to the neutral hole trap becoming unstable during injection, acting as an electron trap. This instability appears to be enhanced as the temperature is reduced to 100 K by a “freeze out’’ effect, or by higher energy carriers that result from a reduction in the thermal scattering. The defect generation rate follows a power law, much like a chemical rate equation, i.e., the rate of defect generation is dependent on the injection current density, much like a chemical reaction is dependent on pressure of the reactive species. The charge centroid of the generated defects, measured from the substrate/oxide interface, was determined at both temperatures and the centroid of the shallow electron traps was determined at 100 K. These were found to be in the range of 6–8 nm at 100 K and 10–16 nm at 293 K. Also, a defect free, or tunneling, region of 2–4 nm extent was determined to exist at each interface. This implies that when the oxide thickness decreases to about 4–8 nm, no threshold voltage shift should result from carrier injection at room, or low temperature, and in fact this behavior was observed in these devices (at least up to 1017 e/cm2 injected). It was found that the shallow traps can be rapidly depopulated by subjecting the devices to ordinary white light during normal device use, pointing to a possible method to improve device reliability at 100 K.

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