Low cost VLSI design of a flexible FFT processor

Abstract

In this paper, a low-cost VLSI implementation of a pipeline fast Fourier transform (FFT) processor capable of supporting from 1k to 32k FFT sizes is presented. The radix-22/23 based pipeline structure reduces the steps of normal complex multiplications, and the single-path delay feedback (SDF) memory access method ensures a minimum (N-1) memory words to get the FFT results. As for the data-path in the pipeline FFT processor, the hybrid floating point data-scaling scheme is adopted to achieve enough signal-to-quantization-noise ratio with minimum data width and RAM requirements. A 1k–32k flexible FFT core is implemented in the Altera FPGA, results show that our proposed scheme is suitable for applications where flexible large size FFT processor is needed such as digital video broadcasting, wireless networks etc.