Low-cost modular testing and test resource partitioning for SOCs

Abstract

The popularity of system-on-chip (SOC) integrated circuits has led to an unprecedented increase in test costs. This increase can be attributed to the difficulty of test access to embedded cores, long test development and test application times, and high test data volumes. A survey is presented of test resource partitioning techniques that facilitate low-cost SOC testing. Topics discussed here include techniques for modular testing of digital, mixed-signal and hierarchical SOCs, as well as test data compression methods for intellectual property cores. Together, these techniques offer SOC integrators with the necessary means to manage test complexity and reduce test costs.