Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling

Abstract

With shrinking device sizes, System-on-Chip (SoC) cores are growing in number and complexity. This has led to high volumes of test data and long test times. Therefore, reducing test cost by minimizing the overall test time is one of the main goals of SoC testing. To efficiently manage test resources and power dissipation, tests for the SoC cores are arranged into test schedules. Traditional SoC test methods assume a constant test frequency and supply voltage (VDD) for the entire test schedule. However, test power and test time can be regulated by varying VDD and test clock frequency to optimize SoC test schedules for a given power budget. The research presented in this paper focuses on power-aware optimization of SoC test schedules to minimize test time by scaling the supply voltage and test clock rate. This scaling can be on a per session basis (in case of session-based test schedules) or dynamically (in case of sessionless test schedules). Exact and heuristic algorithms for solving the optimization problem are discussed. These algorithms are implemented and applied to several SoC benchmarks. Results show a significant reduction in SoC test time over the conventional test schedules where VDD and clock are fixed at given nominal values.