Low Cost Built-in Sensor Testing of Phase-Locked Loop Dynamic Parameters

Abstract

Phase-locked loops (PLLs) serve as core building blocks for communication systems and are often used to synthesize IO clocks for data synchronization and frequency sources for RF conversion. Testing of PLL loop performance is consequently important for guaranteeing the reliability of the underlying communication systems. In this paper, a low cost testing method based on loop triggering and use of built-in analog sensors (small number of transistors) to accurately predict phase-locked loop dynamic parameters is proposed. The sensor responses show strong statistical correlation with the PLL parameters being tested. Accordingly, supervised learning is applied to predict the required PLL parameters from the observed sensor response after "training". In order to verify analog sensor testing in PLL loop response evaluation, an off-the-shelf PLL and a PLL on printed circuit board (PCB) are tested using this method. The results are analyzed and shown with high correlation to loop parameters. Parameters including charge pump current, voltage-controlled oscillator (VCO) gain, bandwidth, phase margin, and locking time are predicted accurately to prove the viability of the proposed test method.