Abstract
This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri- Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by- step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi- parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4- parallel (1020, 990) BCH decoder over GF(2 12 ), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architect- tures.
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