An Efficient Eligible Error Locator Polynomial Searching Algorithm and Hardware Architecture for One-Pass Chase Decoding of BCH Codes

Abstract

In numerous memory and communication systems, Bose–Chaudhuri–Hocquenghem (BCH) codes are widely employed to enhance reliability. A one-pass Chase soft-decision decoding algorithm for BCH codes was previously proposed to achieve significant performance improvement over traditional hard-decision decoding while not increasing too much computational complexity. The bottleneck in conventional one-pass Chase decoding is the procedure of judging whether an obtained error locator polynomial is valid. In this brief, a novel algorithm that can efficiently verify eligibility of each generated error locator polynomial is proposed. The problem is first reformulated as a polynomial modulo problem, where repeated squaring can be employed for further simplification. In order to decrease the critical path delay and hardware complexity, an efficient polynomial division algorithm based on polynomial inversion is also proposed. In addition, a VLSI architecture for the proposed algorithm is presented. The implemented results show that the proposed eligibility checking algorithm reduces the gate counts to only 12% of a conventional polynomial selection algorithm without introducing any speed penalty. The projected area reduction achieved in a complete one-pass Chase decoder is approximately 75%. In addition, post-layout simulation shows that the proposed algorithm is 20 times more power efficient than the conventional method.