Low complexity HEVC sub-pixel motion estimation technique and its hardware implementation

Abstract

In this paper, a low complexity High Efficiency Video Coding (HEVC) sub-pixel motion estimation (SPME) technique is proposed. The proposed technique reduces the computational complexity of HEVC SPME significantly at the expense of slight quality loss by calculating the sum of absolute difference (SAD) values of sub-pixel search locations using the SAD values of neighboring integer pixel search locations. In this paper, an efficient HEVC SPME hardware implementing the proposed technique for all prediction unit (PU) sizes is also designed and implemented using Verilog HDL. The proposed hardware, in the worst case, can process 38 Quad Full HD (3840×2160) video frames per second.