Abstract
High Efficiency Video Coding (HEVC) is the latest video coding standard which aims to provide a much better coding performance than that of its predecessor, namely, H.264, especially for High-Definition (HD) videos. To fulfill such a goal, the Prediction Unit (PU) modes and partitions are more complex and the search range of Motion Estimation (ME) is much larger. As a result, ME becomes a bottleneck during the design of HEVC inter predictor. In view of this, the present paper proposed a fast ME friendly hardware architecture for HEVC encoders based on 2-D data reuse and low-power Sum of Absolute Difference (SAD) tree. By taking advantages of the proposed horizontal and vertical reference SRAMs and SAD tree with PU-level chip selection, this design is quite appropriate for transplanting fast ME algorithms.
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