Low-Complexity FPGA Implementation of 106.24Gbps DP-QPSK Coherent Optical Receiver With Fractional Oversampling Rate Based on One FIR Filter for Resampling, Retiming and Equalizing

Abstract

A novel low-complexity combined resampling, retiming and equalizing (RRE) algorithm is proposed. The RRE algorithm uses a single FIR filter for resampling, retiming and equalizing and thus lower the complexity. In the numerical simulation, with an oversampling rate of 32/27, compared to the traditional time-domain scheme with a 15-tap CMA equalizer and the frequency-domain scheme based on 256-point FFT, the RRE algorithm with a 15-tap RRE filter lowers the error vector magnitude (EVM) by 0.036dB and 0.043dB and the complexity is lowered by 48.3% and 31.9%, respectively. In the offline experiment, with a received optical power of -35dBm, compared to the traditional time-domain scheme with a 15-tap CMA equalizer and the frequency-domain scheme based on 256-point FFT, the RRE algorithm with a 15-tap RRE filter lowers the EVM by 0.26dB and 0.36dB. And the RRE algorithm respectively lowers the complexity by 48.3% and 31.9%. The RRE algorithm also enables a real-time 106.24Gbps (26.56GBaud) DP-QPSK coherent optical receiver based on a single FPGA chip using four 6-bit ADCs with a sampling rate of ∼31.48GSa/s. The FPGA-based receiver achieves a sensitivity of -34dBm at BER of 1E-3. As far as we know, this is the highest reported bit rate of a coherent receiver based on a single FPGA chip.