Low-complexity detection and decoding scheme for LDPC-coded MLC NAND flash memory

Abstract

With the development of manufacture technology, the multi-level cell (MLC) technique dramatically increases the storage density of NAND flash memory. As the result, cell-to-cell interference (CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells. Recently, low-density parity-check (LDPC) codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm (SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio (LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection (N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages. Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliability-based iterative majority-logic decoding (MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.