Abstract
This paper presents a low complexity architecture for a linear periodically time varying (LPTV) filter. This architecture is based on input switching representation of LPTV filters. This representation consists of a bank of linear time invariant (LTI) filters with a periodic switch at the input. Due to the switching operation at the input there will be zeros introduced in the input signals of the LTI filters. These zeros will result in futile multiplications. In this paper we develop an efficient architecture by removing these multiplication operations. This architecture is generalization of direct form. The proposed architecture has been synthesized and implemented on Virtex 2pv30-7ff896 FPGA.
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