Abstract
We explore the performance improvement of ultra-scaled phase-change memory (PCM) device with graphene- Ge2Sb2Te5 (GST) heterostructure by means of first-principle simulations of electron transport. We compare the tunneling probability of single-barrier(SB) and double barrier(DB) heterostructures and show that the use of DB can have a significant impact on the ON/OFF conductance ratio of the device. The reason for this is that the graphene layers in the middle of the single potential barrier, forming the double potential barrier, perform as an operative phase randomizer and destroy the coherence of the electrons that carry out the transport. Hence, the electric current and conductivity decrease in the amorphous phase and the ON/OFF conductance ratio sharply increases. The results of this work offer great potential to obtain a high ON/OFF ratio in ultra-scaled PCM devices.
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