Low and High V t GOTFET Devices Outperform Standard CMOS Technology in Ternary Logic Applications

Abstract

ABSTRACT This work reports low and high threshold gate-overlap tunnel FET (GOTFET) devices for ternary logic applications. An iterative numerical algorithm was developed, which optimises the GOTFET structure such that its characteristics are far superior to the equally-sized MOSFET at the same technology node. These devices are designed in such a way that the low and high (LVT & HVT) are and , respectively, with the ranges (), () & () representing 0, 1 & 2 states, respectively. The performance of the GOTFETs is explained with physical explanations and models of device operation. Optimised GOTFETs were benchmarked with standard MOSFETs for the same circuits designed using the same technology. We have used 45 nm technology for all benchmarking purposes, since it is the lowest industry-standard technology library freely available for academic purposes. Proposed GOTFETs have on currents roughly twice, and off currents at least an order lower than the corresponding MOSFETs. Furthermore, this work proposes a method to effectively suppress the ambipolar behaviour of GOTFETs with improved device performance, engineering the appropriate drain doping concentration, and a gate overlap/underlap on the source and drain regions. The performance of the optimised complementary GOTFET (CGOT) negative ternary inverter (NTI), positive ternary inverter (PTI) & standard ternary inverter (STI) cells were benchmarked with equivalent CMOS circuits. The overall PDP of the CGOT ternary cells were 99.9% lower than the corresponding CMOS cells. The proposed CGOT ternary cells will serve as the starting point for any ternary logic applications.