Abstract
Abstract Room-temperature bias stress measurements were performed on n-type InP MIS capacitors. A wide range of interface passivation processes and gate dielectrics was investigated. A generally observed behaviour under positive bias stress is a slow trapping - fast detrapping consistent with a trap distribution in the interfacial layer above the conduction band edge of InP. Large variations both in the magnitude and in the time dependence of the flat-band voltage shift ΔVFB are observed. We discuss these drift behaviours in terms of interface traps - rather than bulk dielectric traps - in relation with the physico-chemical properties of the interface. It is shown that devices based on InP treated by annealing under arsenic pressure and controlled oxidation exhibit a very good stability. For any passivation procedure, the drift is strongly diminished if the device is stressed with AC voltage compared to DC voltage.
Published Version
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