Abstract
The polynomial time algorithm obtained earlier by the authors is extended to find a minimal cardinality path set that long covers each lead or gate input of a digital logic circuit. It is shown how to find, in polynomial time, a minimal cardinality set MinMaxSP for a given combinational logic circuit. Combinational circuit verification is used to verify the sequential circuit delays.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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