Logic verification of incomplete functions and design error location

Abstract

At the stage of logic verification, it is necessary not only to detect but also to locate the sources of design errors that may exist in the gate-level circuit. For an incompletely specified function, a method to compute the corresponding 3-terminal BDD that represents the ON-set, OFF-set and DC-set, is described. Two incomplete functions are equivalent if, and only if, their 3-terminal BDDs are isomorphic. If the gate-level circuit is verified to be incorrect, a conditional stuck-at fault model is proposed to represent the circuit with design errors. The incorrect logic values at the design error sites can be considered as conditional stuck-at faults. A design error locating method, based on fault simulation and released pattern generation, is described.