Logic synthesis

Abstract

Data-parallel applications are growing in importance and demanding increased performance from hardware. Since the fundamental data structures for a wide variety of data parallel applications are scalar, vector, and matrix, this paper proposes a simple matrix processor (SMP) for executing scalar, vector, and matrix instructions on a unified datapath. Matrix register file and matrix control unit are added to the decode stage of the well-known 5-stage pipeline (baseline scalar processor). To further improve the performance, a simple super-matrix processor (SSMP) is proposed to execute multi-scalar/vector/matrix instructions on parallel execution datapaths. 4×32-bit instructions are fetched, decoded, and checked for dependencies. Up to four independent scalar instructions can be issued in-order to the parallel execution units. However, vector/matrix instructions iterate the issuing of four vector/matrix operations without checking. 4×32-bit contiguous vector/matrix elements can be loaded/stored per clock cycle from/to L2 cache to/from matrix register file, however, scalar data can be accessed from L1 cache in a rate of one element per clock cycle. To prove our concept, the proposed SMP/SSMP are implemented on Xilinx Virtex-6 and evaluated on vector/matrix kernels. 8679/11734 slices are required for implementing SMP/SSMP, where the complexities are 2.79/3.77 times higher than the baseline scalar processor. However, the speedups of SMP/SSMP over the baseline scalar processor are 1.57-6.33/4.32-18.23.