Abstract
A logic simulation tool for RSFQ circuits is proposed. It can treat RSFQ logic circuits containing signal lines accepting multiple pulses in a clock period. Logic circuits can be implemented in compact area by utilizing RSFQ specific gates and feeding multiple pulses into a gate input in a clock period. For treating circuits containing signal lines accepting multiple pulses in a clock period, a new description method is proposed. A logic simulation tool treating netlists described based on the proposed method was implemented. Examples of designs having signal lines accepting multiple pulses to be implemented in compact area are shown, and simulation results obtained with the tool are shown.
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