An implementation of multiple‐valued logic circuit with cmos multiple‐valued output gates

Abstract

AbstractWith the progress of high‐density information handling technology, multiple‐valued logic is considered interesting. Studies have been made on the applications to the high‐density VLSI and the optimally multiple‐valued information processing systems. This paper considers the use of a CMOS multiple‐valued output gate, and proposes an implementation of the multiple‐valued logic circuit, which is suited to the integration from the viewpoints of the integration density and the power consumption. The CMOS multiple‐valued output gate produces a multiple‐valued output from the predetermined number (n ‐ 1 for n‐valued case) of binary inputs. Compared with similar multiple‐level output circuits proposed up to now, the gate has the feature of simple structure and easy correspondence to arbitrary n‐valued function. In the design of the multiple‐valued logic circuit by the proposed method, the inputs to the multiple‐valued output gate are determined first from the required multiple‐valued output. Then the logic circuit satisfying the inputs is constructed from the literal circuit with multiple‐valued inputs and binary logic circuits. Design examples by the proposed method are presented. It is shown especially for the arbitrary n‐valued case that the design is simplified since the inputs to the multiple‐valued output gate can be represented in the general form. Several rules for deriving the general form are described. Finally, it is made possible to implement the multiple‐valued logic circuit, which is simple and suited to integration.