Logic for static hazard detection of multiple-valued logic circuits with TSUM, MIN, and Literals

Abstract

Multiple-valued logic circuits are often implemented by the current mode CMOS technology, or sometimes the voltage mode technology. Even if multiple-valued logic circuits are realized by either one of the two technologies, the signal propagation delay will cause hazards pluses, which are undesirable short pulses in circuits. This paper will focus on static hazards in multiple-valued logic circuits. The paper is supposed to have a device technology such as the current mode CMOS technology, because the way of information signals transition is very important to introduce a logical model for hazards detection of multiple-valued logic circuits. We will show some of the mathematical properties of functions on the logical model introduced by the paper. Multiple-valued logic circuits are supposed to be constructed by the truncated sum, the minimum, and the literal gates.