Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing

Bahman Kheradmand-Boroujeni,Christian Piguet,Yusuf Leblebici

doi:10.1007/978-3-642-17752-1_17

Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing

Bahman Kheradmand-Boroujeni, Christian Piguet + Show 1 more

https://doi.org/10.1007/978-3-642-17752-1_17

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Publication Date: Jan 1, 2011

Citations: 1

Affiliation: École Polytechnique Fédérale de Lausanne, Swiss Center for Electronics and Microtechnology (Switzerland)

#Process Variations #Random Process Variations + Show 8 more

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Abstract

We show that in logic circuits working at supply voltage (VDD) below nominal value, proper selection of logic architecture and VDD together can reduce the impact of device-to-device random process variations (PV) on timing. First we show that σ/µ of transistor current and delay strongly depend on VDD. Then we compare the PV sensitivity of Low-Power Slow (LP-S) and High-Power Fast (HP-F) architectures. The results propose the idea that for a given technology, equal power budget and delay, LP-S circuits working at higher VDD are about 1.8X less PV sensitive compare to HP-F circuits working at lower VDD.

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