Logic and memory characteristics of an inverter comprising a feedback FET and a MOSFET

Abstract

In this study, we design an inverter comprising a p-channel feedback field-effect transistor (p-FBFET) and an n-channel metal-oxide-semiconductor field-effect transistor and examine its logic and memory characteristics. For the transition of inverter from the logic ‘0’ (‘1’) state to ‘1’ (‘0’) state, the gain is 2001.6 V/V (1992.4 V/V). The steep switching characteristics and high on/off current ratio of the p-FBFET contribute to the high inverter gains. For an inverter with zero static power consumption, the logic states remain for more than 500 s. The long retention time allows the inverter proposed in this study to be applicable to logic-in-memory.