Abstract
This paper presents a novel method for locating combinational hardware Trojans (HT) based on fault location approaches used in combinatorial testing. This method relies exclusively on the combinatorial properties of the executed test vectors and the results of test execution. Under specific assumptions, the method is guaranteed to locate all combinational HTs with trigger patterns of length <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\ell $ </tex-math></inline-formula> or less, with the location process itself consuming negligible time. We give a description of our method by devising suitable algorithms and provide the links to combinatorial fault location. Furthermore, we demonstrate our approach in a concrete case study where we locate HTs embedded in a circuit that implements the AES symmetric-key encryption algorithm with 128 bits key length. In these experiments, we demonstrate how any HT that is activated by a trigger pattern of length <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\ell \leq 8$ </tex-math></inline-formula> can be located in an effective way. Our method compares particularly well against randomized approaches. Although instantiated for a specific circuit in our case study, the proposed approach is generic, due to its algorithmic description, and can be applied for testing other (cryptographic) circuits. We believe that our work presents an important first step in the development of more general logic testing methodologies for HT location using combinatorial testing methods.
Highlights
The security of information and communication technologies and electronic systems in general is often solely related to the security of its software part, leaving hardware security out
One of the most severe and threatening attacks to an IC is the integration of a hardware Trojan, a malicious modification to fieldprogrammable gate arrays (FPGAs), application-specific integrated circuits (ASICs), microprocessors or IoT devices [9], [10]
CONTRIBUTION In this paper, we introduce a novel logic testing methodology based on combinatorial fault location methods that can excite and locate hardware Trojans that are triggered by certain combinational bit patterns in the primary input
Summary
The security of information and communication technologies and electronic systems in general is often solely related to the security of its software part, leaving hardware security out. One of the most severe and threatening attacks to an IC is the integration of a hardware Trojan (abbreviated as HT or Trojan for short), a malicious modification to fieldprogrammable gate arrays (FPGAs), application-specific integrated circuits (ASICs), microprocessors or IoT devices [9], [10]. Such modifications can change the functionality of the hardware, e.g. downgrade its performance or provide a backdoor through which sensitive information can be leaked. We believe that the covering and separating properties of detecting arrays (considered in combinatorial testing) will positively influence the future development of HT location techniques
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