Abstract

Metallization of through silicon vias (TSVs) used for the wafer interconnection in three-dimensional integration possess usually a certain amount of tensile residual stresses which originate from the mismatch of the coefficients of thermal expansion between the metal and silicon. In this contribution, novel experimental approaches based on the synchrotron X-ray nanodiffraction and Raman spectroscopy are used to determine residual stresses in tungsten coated TSVs, in the metal as well as in the surrounding silicon. The results indicate that the stresses in silicon surrounding the TSVs are relatively negligible but the stress state in the tungsten film can be high. Moreover, the ripple-like morphology of the tungsten thin film results in the stress magnitude oscillations across the via wall. Finally, the complementary X-ray and Raman approaches document that both techniques can serve as an effective tool to monitor the stress state with a spatial resolution down to 100nm and to analyze degradation effects caused by the thermal and mechanical constrains in the chip.

Full Text
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