Abstract
Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon continues its investigation of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications also preliminary data illustrating 450 mm wafer process challenges.
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