Linearity improvement of open-loop NMOS source-follower sample and hold circuits

Abstract

A new open-loop sample and hold (S/H) circuit is proposed for high-speed sampled data applications. The open-loop S/H circuit uses the source-follower configuration, for its high speed, low power consumption, small area and low circuit complexity. In order to achieve high linearity, a body effect cancellation technique is proposed which is based on proper modulation of the bias current of the source-follower transistor. Simulated by HSPICE with a standard BSIM3v3 0.18 μm CMOS technology, the pseudo-differential open-loop S/H achieves over 76 dB spurious free dynamic range (SFDR) for a 1.6 V ppd output at 200 MHz sampling frequency. The S/H dissipates 12.5 mW power from a 1.8 V supply.