Linear finite state machine for lD ILAs

Abstract

Linear Finite State Machine for One Dimensional (1D) Iterative Logic Arrays (ILAs) is described. The technique for modifying the Linear Feedback Shift Register (LFSR) based test generator called Linear Finite State Machine (LFSM) for deterministic test pattern generation is discussed and extended for generating the test vectors for 1D unilateral ILAs. One Repetition Length (ORL) of C-testable ILAs and unique characteristics of the C-testable test patterns are used for the compact design of the LFSM based at-speed Built-in Self Test (BIST). Such LFSM based BIST occupies small silicon area, simplifies the design of the controller and does at-speed testing of the ILAs. This results in reduced time and cost of testing. In addition, the exact probability distribution equations are developed for additional bits needed to map a Finite State Machine (FSM) into an LFSM. The distribution clearly shows that the expected number of additional bits is very small, often zero. The probability distribution equations are equally valid for any LFSR based test generator for other circuits. >