Abstract
WDM and TDM systems are compared for the next generation of line terminating multiplexers operating at around 10 Gb/s. A byte-interleaving circuit configuration suitable for large-scale synchronous multiplexing in multiples of eight is proposed. A prototype terminal circuit for STM-64 multiplexing that uses BiCMOS, Si bipolar, and GaAs MESFET IC technologies is reported. >
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