Line resistance behaviour in narrow lines patterned by a TiN hard mask spacer for 45 nm node interconnects

Abstract

The down scaling of interconnect wiring is facing serious hurdles below 100 nm feature size due to a non-linear resistivity increase with decreasing line width. Moreover, the use of porous low-k dielectrics in combination with narrow line dimensions could lead to metallization problems related to the non-conformality of the barrier-seed deposition. Therefore, the effect of line size on the resistivity increase has been investigated in a multitude of sub 100 nm lines patterned in a porous low-k dielectric. The damascene copper lines were fabricated with a novel patterning approach upon using a CVD TiN hard mask spacer. The narrowest lines of 50 nm showed a 50% increase of the resistivity compared to the copper bulk resistivity (1.8 μΩcm). The experimental data were compared to a theoretical model that includes diffusive scattering of electrons at the grain boundaries and at the surface of the wire. A good agreement was found between the data and the model. The model shows a good specular reflection of electrons on the side wall although a porous low-k material was used.