Least squares approximation-based ROM-free direct digital frequency synthesizer

Abstract

This paper describes a new design approach and an architecture for a direct digital frequency synthesizer (DDFS) based on least square (LS) approximation. It is shown that the architecture can be implemented as a low-cost, low-power, feedforward, and easily pipelineable datapath. A prototype IC has been designed and fabricated in TSMC 0.25 /spl mu/m CMOS technology. The IC produces 14-bit sine and cosine outputs with a spurious free dynamic range of 100 dBc. A 32-bit frequency word gives a tuning resolution of 0.0466 Hz at 200 MHz sampling rate.