Leakage-proof domino circuit design for deep sub-100 nm technologies

Abstract

The leakage power consumption in deep sub-100 nm CMOS systems is projected to become a significant part of the total power dissipation. Although the dual Vt CMOS process helps reduce the subthreshold leakage current in domino circuits, the gate leakage problem poses a significant design challenge. We propose two new circuit techniques to suppress both subthreshold leakage current and gate leakage current in domino circuits. In standby mode, subthreshold leakage current is suppressed by using dual Vt devices in the two proposed circuits. The proposed circuits generate low inputs and low outputs to suppress gate leakage current in the NMOS logic tree in standby mode. Simulation results based on 45 nm BSIM4 models show that 32-bit adders using the two proposed circuits can reduce the total standby leakage by 83.2% and 93.2%, respectively, compared with the adder using single Vt domino circuits. Proposed adders have 7% active power overhead to achieve the same speed as single Vt domino adder and the area penalty is minimal with careful layout.