Leakage studies in high-density dynamic MOS memory devices

Abstract

The authors describe an in-depth study of leakage sources in dynamic MOS memory devices. It is shown that special device structures may be fabricated to separate and understand the nature of leakage from periphery and bulk. The periphery leakage is due to the transition region of gate-to-field oxide overlapped by the gate electrode. This contribution can be up to 10/spl times/ the contribution due to classical surface and bulk generation under the storage electrode itself. It is also shown that with increased bulk lifetime in state-of-the-art devices, the diffusion component of leakage becomes very significant, especially at high temperatures. These studies lead to device design criteria from leakage considerations that will be very important for VLSI memory design.