Leakage power reduction in multicore chips via online decap modulation

Abstract

The decap leakage constitutes a significant part of total leakage in multicore processors. Leaking decap is widely used in chips to provide transient power to function blocks, and the amount of decap placed over multicore chip is determined by the worst case at design time. Considering that the decaps do not have to be kept 100% when the chip is running workloads, in this paper we propose an ideal online approach to adapt the percentage of capacitance in the decaps to the dynamic need of the core loads, and therefore to reduce the leakage power consumption in the chip. Our approach is based on the equivalent resistance model of the power sources (power supply pins and local decaps) and the core loads, and a novel fast algorithm is developed to determine the required amount of decap at runtime. Results on a set of multicore test cases show that our approach can achieve up to 48% saving in decap leakage.